2x2 Combinational Multiplier
DSP accelerators and ALUs rely on hardware multipliers to execute multiply-accumulate operations in a single clock cycle. Instead of repeated addition, these units use a massive combinational array to compute and sum partial products simultaneously.
The circuit must multiply a 2-bit input A by a 2-bit input B to produce a 4-bit product P.
| A | B | P | |-----|-----|------| | 00 | 00 | 0000 | | 00 | 01 | 0000 | | 00 | 10 | 0000 | | 00 | 11 | 0000 | | 01 | 00 | 0000 | | 01 | 01 | 0001 | | 01 | 10 | 0010 | | 01 | 11 | 0011 | | 10 | 00 | 0000 | | 10 | 01 | 0010 | | 10 | 10 | 0100 | | 10 | 11 | 0110 | | 11 | 00 | 0000 | | 11 | 01 | 0011 | | 11 | 10 | 0110 | | 11 | 11 | 1001 |
Constraints
- Combinational logic only.
- Do not use high-level multiplication blocks or operators.
- Construct the array using only 2-input AND gates and Half Adders.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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