4:16 Decoder from 2:4 Decoders

Large memory arrays rely on hierarchical row decoders to select specific wordlines without requiring massive fan-in logic gates. A 4:16 decoder constructed from smaller 2:4 decoders demonstrates the fundamental two-level tree architecture used in SRAM and DRAM address decoding.

The circuit takes a 4-bit address input A3, A2, A1, and A0 and asserts exactly one of the 16 output lines Y15 through Y0. The most significant bits A3 and A2 determine which block of four outputs is active. The least significant bits A1 and A0 select the specific output within that active block. All inactive outputs must be driven to 0.

| A3 | A2 | A1 | A0 | Active Output (= 1) | |------|------|------|------|-----------------------| | 0 | 0 | 0 | 0 | Y0 | | 0 | 0 | 0 | 1 | Y1 | | 0 | 0 | 1 | 0 | Y2 | | 0 | 0 | 1 | 1 | Y3 | | 0 | 1 | 0 | 0 | Y4 | | 0 | 1 | 0 | 1 | Y5 | | 0 | 1 | 1 | 0 | Y6 | | 0 | 1 | 1 | 1 | Y7 | | 1 | 0 | 0 | 0 | Y8 | | 1 | 0 | 0 | 1 | Y9 | | 1 | 0 | 1 | 0 | Y10 | | 1 | 0 | 1 | 1 | Y11 | | 1 | 1 | 0 | 0 | Y12 | | 1 | 1 | 0 | 1 | Y13 | | 1 | 1 | 1 | 0 | Y14 | | 1 | 1 | 1 | 1 | Y15 |

Constraints

• Construct the circuit using exactly five 2:4 decoders.
• Use one 2:4 decoder as a pre-decoder driven by A3 and A2 to generate four enable signals.
• Use the remaining four 2:4 decoders to drive outputs Y15 through Y0.
• Drive the select inputs of all four output decoders using A1 and A0.
• Do not use any additional logic gates outside of the decoders.

Topics

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