4-Bit Overflow Detector
Arithmetic logic units must alert the system processor when the result of a signed addition exceeds the representable range. This detection prevents catastrophic calculation errors in software by triggering hardware exception handlers.
The circuit receives a 4-bit augend A, a 4-bit addend B, and an initial carry Cin. It must compute the 4-bit sum S and a 1-bit Overflow flag. The Overflow signal must assert high when the two's complement addition result falls outside the valid 4-bit range of -8 to +7.
| A | B | Cin | S | Overflow | |------|------|-------|------|------------| | 0111 | 0000 | 0 | 0111 | 0 | | 0111 | 0001 | 0 | 1000 | 1 | | 1000 | 1111 | 0 | 0111 | 1 | | 1111 | 1111 | 0 | 1110 | 0 |
Constraints
- Combinational logic only.
- Derive the
Overflowsignal strictly from the internal carry chain of the adder. - Do not use magnitude comparators or output sign-bit checking logic.
Topics
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