4-Bit Ripple Carry Adder
Arithmetic logic units and address calculation stages rely on multi-bit adders to compute offsets and sums. The ripple carry adder cascades single-bit adders to process wider words sequentially.
The circuit must compute the sum of two 4-bit inputs A and B. The carry-in to the least significant bit must be permanently tied to logic 0. The carry-out of each stage must propagate directly to the carry-in of the next most significant stage. The final output consists of a 4-bit sum S and a 1-bit carry-out Cout.
| A | B | S | Cout | |-----|-----|-----|--------| | 0 | 0 | 0 | 0 | | 5 | 4 | 9 | 0 | | 7 | 1 | 8 | 0 | | 15 | 1 | 0 | 1 | | 10 | 12 | 6 | 1 |
Constraints
- Use exactly four Full Adder blocks.
- The carry-in of the least significant bit must be connected to a constant 0.
- Combinational logic only.
Topics
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