4-bit Equality Comparator (Gate-Level)
Equality comparators are among the most frequently used combinational circuits in real hardware. Address decoders in memory systems use them to check if the CPU's address matches a peripheral's base address. Cache tag comparison uses equality to determine a hit or miss. Every time two buses are checked for identical content, an equality comparator is at work.
Your task is to build a 4-bit equality comparator. Given two 4-bit inputs — A (bits A3 down to A0) and B (bits B3 down to B0) — the output EQ is 1 if and only if A and B are identical. EQ is 0 if any corresponding bit pair differs.
A and B are equal when A3=B3, A2=B2, A1=B1, and A0=B0 simultaneously. Each bit comparison is an XNOR operation (outputs 1 when the two inputs are equal). The final EQ is the AND of all four XNOR results. Since XNOR is not directly available in LOGIX, implement each XNOR as XOR followed by NOT. Then reduce the four results through a chain of AND operations.
Worked examples: if A = 1010 (A3=1, A2=0, A1=1, A0=0) and B = 1010 (B3=1, B2=0, B1=1, B0=0), then EQ = 1. If A = 1010 and B = 1110 (B2=1), then bit 2 differs and EQ = 0.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A3 | input | 1 | MSB of input A | | A2 | input | 1 | Bit 2 of input A | | A1 | input | 1 | Bit 1 of input A | | A0 | input | 1 | LSB of input A | | B3 | input | 1 | MSB of input B | | B2 | input | 1 | Bit 2 of input B | | B1 | input | 1 | Bit 1 of input B | | B0 | input | 1 | LSB of input B | | EQ | output | 1 | 1 when A equals B, 0 when any bit pair differs |
Constraints
- The circuit is purely combinational. No clock or state.
- Any gate types from the LOGIX component set are allowed.
- The optimal solution (7 components) uses 4 XOR + 3 gates for reduction. An equivalent approach using De Morgan: XOR all four bit-differences, OR the results, then NOT — same gate count.
- All 256 combinations of A and B are valid inputs; the circuit must be correct for all of them.
Topics
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