8-Bit Cascaded Magnitude Comparator
Address decoding, sorting networks, and branch condition evaluation rely on wide magnitude comparators to determine the relationship between data words. Standard discrete ICs and ASIC libraries provide 4-bit comparator primitives that must be chained together to evaluate wider buses.
Construct an 8-bit magnitude comparator that compares an 8-bit unsigned input A against an 8-bit unsigned input B. The circuit must drive three outputs: GT when A is greater than B, EQ when A is equal to B, and LT when A is less than B. The lower block processes bits 3 to 0, and its outputs feed the cascade inputs of the upper block processing bits 7 to 4.
| A | B | GT | EQ | LT | |-----|-----|------|------|------| | 10 | 10 | 0 | 1 | 0 | | 10 | 9 | 1 | 0 | 0 | | 9 | 10 | 0 | 0 | 1 | | 255 | 0 | 1 | 0 | 0 |
Constraints
- Use exactly two 4-bit magnitude comparator blocks.
- Route the cascade outputs of the lower block into the cascade inputs of the upper block.
- Tie the cascade inputs of the lower block to represent strict equality.
Topics
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