Absolute Value Circuit Sharing
Computing the absolute value of signed signals is a frequent operation in digital signal processing, particularly in magnitude estimation and error calculation. A naive implementation infers a full adder for twos complement negation followed by a wide multiplexer to select between the original and negated values.
To minimize cell area, the circuit can share the adder logic. Instead of computing the negation and then multiplexing, the input is conditionally inverted based on its sign bit. If the number is negative, all bits are inverted; if positive, they remain unchanged. The sign bit is then added as a carry in to complete the twos complement operation for negative numbers, while adding zero for positive numbers. This architecture avoids the wide multiplexer entirely.
This is a purely combinational circuit. Outputs must reflect the inputs continuously without any clock or reset dependency.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Signed twos complement input | | abs_a | output | 8 | Unsigned absolute value of the input |
Constraints
- The circuit must be purely combinational with no latches or flip-flops.
- You must use conditional bitwise inversion and a single addition step rather than a conditional operator to select between the input and its negation.
- The most negative input value of 128 in twos complement must correctly result in an unsigned output of 128.
Topics
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