Adder Resource Sharing
Area constraints in ASIC and FPGA design often dictate that expensive arithmetic blocks be shared across multiple datapaths. When a datapath needs to compute either $A+B$ or $C+D$ based on a control signal, a naive RTL implementation will instantiate two separate adders and multiplex their outputs, wasting expensive silicon area.
The module solution receives four 8-bit unsigned operands (a, b, c, d) and a single control bit (sel). When sel is 1, the module computes the sum of a and b. When sel is 0, the module computes the sum of c and d.
This is a purely combinational circuit. The critical requirement is that the RTL must force the synthesis tool to infer exactly one adder. To achieve this, the inputs must be multiplexed before the addition operation occurs.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | sel | input | 1 | Control signal; 1 selects a and b, 0 selects c and d | | a | input | 8 | First operand for sel=1 | | b | input | 8 | Second operand for sel=1 | | c | input | 8 | First operand for sel=0 | | d | input | 8 | Second operand for sel=0 | | result| output | 9 | Sum of the selected operands |
Constraints
- Combinational logic only; no clock or reset inputs are present.
- Output
resultis 9 bits wide to accommodate the maximum possible sum of two 8-bit unsigned integers without overflow. - The design must synthesize to exactly one adder. The grader will analyze the netlist and fail any submission containing multiple adders.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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