Always Comb Sensitivity Inference

Complex combinational logic often relies on helper functions to keep code readable and modular. However, classic Verilog sensitivity lists struggle to infer dependencies hidden inside these functions, leading to catastrophic simulation mismatches where the circuit fails to update when a hidden variable changes. SystemVerilog solves this by guaranteeing deep sensitivity inference.

The module computes an 8-bit output based on a 1-bit mode signal. When mode is 0, the module outputs the sum of two 8-bit values, val1 and val2. When mode is 1, the module passes val1 through a helper function named apply_mask. This function must take a single 8-bit argument and return that argument bitwise ANDed with the module's mask input, then added to the module's offset input. Crucially, the function must read the mask and offset signals directly from the module scope, not via passed arguments.

This is a purely combinational circuit. There is no clock or reset. The output must update immediately whenever any input changes, including the mask and offset signals read inside the function. All inputs and outputs are unsigned. Any overflow during addition should wrap around the 8-bit boundary.

Step 1: mode=0, val1=10, val2=20 → result=30 (Addition mode) Step 2: mode=1, val1=171, mask=15, offset=1 → result=12 (Function mode applies mask and offset) Step 3: mode=1, val1=171, mask=15, offset=5 → result=16 (Updates immediately when offset changes)

{ "signal": [
  { "name": "mode",   "wave": "=====", "data": ["0", "1", "1", "1", "0"] },
  { "name": "val1",   "wave": "=====", "data": ["10", "171", "171", "255", "200"] },
  { "name": "val2",   "wave": "=====", "data": ["20", "0", "0", "0", "100"] },
  { "name": "mask",   "wave": "=====", "data": ["0", "15", "15", "240", "0"] },
  { "name": "offset", "wave": "=====", "data": ["0", "1", "5", "0", "0"] },
  {},
  { "name": "result", "wave": "=====", "data": ["30", "12", "16", "240", "44"] }
], "head": { "text": "Combinational updates reflecting hidden function sensitivities." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | mode | input | 1 | Selects between addition (0) and masked operation (1) | | val1 | input | 8 | First operand | | val2 | input | 8 | Second operand (used when mode is 0) | | mask | input | 8 | Mask value read inside the function | | offset | input | 8 | Offset value read inside the function | | result | output | 8 | Combinational output |

Constraints

• Must use SystemVerilog always_comb for the main logic block
• Must define and use a function named apply_mask that takes exactly one 8-bit argument
• The function must directly read mask and offset from the module scope without them being passed as arguments
• All operations are purely combinational; no clocks or latches
• Overflows in addition wrap around the 8-bit boundary

Topics

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