Asynchronous Reset Synchronous Deassertion

Digital systems spanning multiple clock domains often rely on asynchronous resets to guarantee a safe initial state without requiring an active clock. However, releasing an asynchronous reset precisely at the active clock edge violates recovery time, triggering metastability across the domain. A reset synchronizer bridges this gap by asserting the reset asynchronously to the entire domain, but de-asserting it synchronously with the clock.

The solution module receives an external asynchronous active-low reset and produces a synchronized active-low reset. When the external reset drops to 0, the synchronized output must drop to 0 immediately, bypassing any clock requirements. When the external reset rises to 1, the synchronized output must remain at 0 until it propagates through a two-stage flip-flop chain, ensuring safe synchronous release.

Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low • Output on reset: rst_s_n goes to 0 immediately when rst_a_n is 0 • Output registered: Yes, rst_s_n is the direct output of the second flip-flop stage

Cycle-by-cycle trace: Cycle 1: rst_a_n=0 → rst_s_n=0 (Asynchronous assertion) Cycle 2: rst_a_n=1, clk pulses once → rst_s_n=0 (First stage captures 1, second stage captures 0) Cycle 3: rst_a_n=1, clk pulses again → rst_s_n=1 (Second stage captures 1, de-assertion complete)

{ "signal": [
  { "name": "clk",     "wave": "001010" },
  { "name": "rst_a_n", "wave": "101..." },
  { "name": "rst_s_n", "wave": "10..1." }
], "head": { "text": "Asynchronous assertion followed by two-stage synchronous de-assertion." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_a_n | input | 1 | Asynchronous active-low reset input | | rst_s_n | output | 1 | Synchronized active-low reset output |

Constraints

• Output rst_s_n must assert asynchronously to 0 immediately when rst_a_n becomes 0.
• Output rst_s_n must de-assert synchronously on posedge clk.
• The synchronizer must use exactly two flip-flop stages.
• The data input to the first flip-flop stage must be permanently tied to logic 1.

Topics

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