Balanced Adder Tree Forcing
High-speed digital signal processing paths frequently accumulate multiple wide operands in a single clock cycle. When an engineer writes a continuous addition chain in Verilog, synthesis tools default to evaluating the expression strictly from left to right. This creates a linear cascade of adders where the carry propagation delay stacks sequentially, severely limiting the maximum clock frequency of the system.
The module computes the sum of four 16-bit unsigned operands. The platform's synthesis backend will analyze the structural netlist of your submission. A standard linear addition chain will fail the timing check. You must structure your RTL to force a balanced tree topology, reducing the critical path from three sequential adder delays to two.
Since this module is purely combinational, there is no clock or reset signal. The output must reflect the sum of the inputs immediately.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 16 | First unsigned operand | | b | input | 16 | Second unsigned operand | | c | input | 16 | Third unsigned operand | | d | input | 16 | Fourth unsigned operand | | sum | output | 18 | Unsigned sum of all four inputs; width prevents overflow |
Constraints
- The design must be purely combinational.
- The output
summust be exactly 18 bits wide to accommodate the maximum possible value without overflow. - The platform synthesis checker will fail the submission if the critical path exceeds two 16-bit adder delays.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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