Bidirectional Port Synthesis
An internal port controller replaces legacy tri-state buses with dedicated input and output paths for modern synthesis.
Expected behavior:
| Dir | WriteData | ReadDataExt | PadOE | PadOut | ReadDataInt | |-------|-------------|---------------|---------|----------|---------------| | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | 1 | | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | | 1 | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 1 | 1 | 1 | 1 |
Simulation shows ReadDataInt = 0 for inputs Dir = 1, WriteData = 1, ReadDataExt = 0. The internal read data fails to reflect the driven output during a write cycle. Inspect the circuit and correct the fault.
Constraints
- Do not use tri-state buffers.
- Output
PadOEmust exactly trackDir. - Output
PadOutmust exactly trackWriteData.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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