Binary Encoding Flip Flop Count

EasyVerilog / SystemVerilogBuild

Hardware designers must balance register usage against combinational logic depth. For state machines with many states, binary encoding minimizes the number of flip-flops required, whereas one-hot encoding uses one flip-flop per state. A 7-state machine requires exactly 3 flip-flops when binary encoded, but requires additional combinational logic to decode the next state and handle wrap-around conditions.

Design a 7-state finite state machine (FSM) using binary encoding. The states proceed in a linear sequence from 0 to 6, then wrap around to 0. The FSM advances to the next state only when the enable signal is asserted. The module must output the current 3-bit binary state directly.

Clock edge: posedge
Reset: Asynchronous active-low reset rst_n. When rst_n is 0, the state resets to 3'b000.
Enable: When en is 1, the FSM transitions to the next state on the clock edge. When en is 0, the FSM holds its current state.
Sequence: 0 → 1 → 2 → 3 → 4 → 5 → 6 → 0.
Recovery: If the FSM enters the invalid state 3'b111, it must transition to 3'b000 on the next active clock edge.

Worked Trace: Cycle 1: rst_n=0, en=0 → state_out=0 Cycle 2: rst_n=1, en=1 → state_out=1 Cycle 3: rst_n=1, en=1 → state_out=2 Cycle 4: rst_n=1, en=0 → state_out=2 (hold) Cycle 5: rst_n=1, en=1 → state_out=3 Cycle 6: rst_n=1, en=1 → state_out=4 Cycle 7: rst_n=1, en=1 → state_out=5 Cycle 8: rst_n=1, en=1 → state_out=6 Cycle 9: rst_n=1, en=1 → state_out=0 (wrap) Cycle 10: rst_n=1, en=1 → state_out=1

flowchart LR
    RESET(( )) -->|reset| S0
    S0((0)) -->|en=1| S1((1))
    S0 -->|en=0| S0
    S1 -->|en=1| S2((2))
    S1 -->|en=0| S1
    S2 -->|en=1| S3((3))
    S2 -->|en=0| S2
    S3 -->|en=1| S4((4))
    S3 -->|en=0| S3
    S4 -->|en=1| S5((5))
    S4 -->|en=0| S4
    S5 -->|en=1| S6
    S5 -->|en=0| S5
    S6(["6 ★"]):::out -->|en=1| S0
    S6 -->|en=0| S6
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

{ "signal": [
  { "name": "clk",       "wave": "p........." },
  { "name": "rst_n",     "wave": "01........" },
  { "name": "en",        "wave": "0110111111" },
  {},
  { "name": "state_out", "wave": "===.======", "data": ["0", "1", "2", "3", "4", "5", "6", "0", "1"] }
], "head": { "text": "FSM counting up to 6, holding, and wrapping around." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; state goes to 3'b000 | | en | input | 1 | Enable signal; advances state when 1 | | state_out | output | 3 | Current FSM state; valid range 0 to 6 |

Constraints

Clock must be positive-edge triggered.
Reset must be asynchronous and active-low.
The design must infer exactly 3 flip-flops.
The FSM must wrap from state 6 directly to state 0.
If the FSM enters the invalid state 3'b111, it must transition to 3'b000 on the next active clock edge.

Topics

FSMState MachineBinary Encoding

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