Blocking Assignment in Sequential Logic
A three-stage pipeline synchronizes the input signal D by delaying it across three clock cycles before outputting to Q.
Expected behavior:
| Cycle | D | Q | |-------|-----|-----| | 1 | 1 | 0 | | 2 | 0 | 0 | | 3 | 1 | 0 | | 4 | 0 | 1 |
Simulation shows Q = 1 at Cycle 2 when D = 1 at Cycle 1. The datapath latency is one clock cycle instead of three. Inspect the circuit and correct the fault.
Constraints
- Circuit must contain exactly three sequential storage elements.
- Output
Qmust strictly follow a three-cycle delay.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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