Case Statement Multiplexer
Data routing networks in ASICs require balanced propagation delays to avoid timing violations. When selecting one of multiple data sources, a balanced multiplexer tree ensures that all input paths have identical logical depth. Writing cascaded conditional statements often forces the synthesis tool to infer a priority encoder, which creates a long critical path for the last evaluated input. A parallel structure inferred from a case statement guarantees symmetric timing across all data paths.
The solution module acts as a 4-to-1 data multiplexer. It routes one of four 8-bit input data buses to a single 8-bit output bus based on a 2-bit selection signal. The mapping is strictly parallel: each value of the selection signal maps directly to a specific input bus.
This is a purely combinational circuit. There is no clock and no reset. The output must reflect the selected input immediately based on the current value of the select signal.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | sel | input | 2 | Selection control signal | | a | input | 8 | Data input 0; selected when sel is 2'b00 | | b | input | 8 | Data input 1; selected when sel is 2'b01 | | c | input | 8 | Data input 2; selected when sel is 2'b10 | | d | input | 8 | Data input 3; selected when sel is 2'b11 | | out | output | 8 | Selected data output |
Constraints
- The design must be purely combinational; do not infer any latches or flip-flops.
- All four discrete states of the 2-bit
selsignal must be explicitly handled. - The output must continuously reflect the input selected by
sel.
Topics
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