Casex Danger
Many digital design houses strictly ban the casex statement in their RTL coding guidelines. While intended to simplify pattern matching, casex introduces severe risks by masking uninitialized logic states during simulation that will ultimately fail in physical silicon.
The snippet below represents an address decoder using a casex statement to match a 4-bit addr input. The designer expects the default case to catch any unmapped addresses. During simulation, an upstream bug causes an uninitialized signal to feed into the lowest bit of addr, causing the expression to evaluate as 4'b101X. One of the valid case items in the block is written as 4'b1011.
Determine how the simulator and the synthesis tool interpret this input differently. Identify the resulting hardware mismatch and the correct alternative construct.
Constraints
- Assume standard IEEE 1364 Verilog semantics for
casexandcasez. - Assume the synthesis tool, such as Yosys, optimizes away
XandZstates as unreachable in physical hardware. - Physical hardware evaluates only to logic 0 or logic 1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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