Casez Leading Zero Counter
Floating-point normalization circuits and fast interrupt controllers rely on finding the most significant asserted bit in a vector with minimal gate delay. A leading zero counter performs this exact function, determining how many zero bits precede the first logic-1 bit from the most significant bit down to the least significant bit.
The module receives an 8-bit input vector and computes the number of leading zeros. If bit 7 is 1, the output is 0. If bit 7 is 0 and bit 6 is 1, the output is 1, continuing downwards to bit 0. If all bits are 0, the output is 8. Using a casez statement with wildcard characters allows the synthesis tool to infer a highly optimized priority routing structure without deep, verbose conditional trees.
This is a purely combinational circuit. Changes on the input must reflect immediately on the output. There is no clock and no reset.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in | input | 8 | Input data vector to be analyzed | | zeros | output | 4 | Number of leading zeros; evaluates from bit 7 down to bit 0; range is 0 to 8 |
Constraints
- Output
zerosmust evaluate to 8 wheninis completely zero. - The design must be purely combinational; no registers or latches are permitted.
- The output must cover the full range of 0 to 8, requiring a 4-bit width.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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