Clock Gating Cell Inference

Power consumption in modern ASICs is heavily dominated by the clock tree. To reduce dynamic power, engineers disable the clock to inactive registers using clock gating. However, simply using an AND gate to combine a clock and an enable signal creates dangerous glitches if the enable signal toggles while the clock is high. Standard cell libraries provide Integrated Clock Gating (ICG) cells to solve this, which synthesis tools can automatically infer if the RTL is written correctly.

The module receives a continuous clock signal clk and a control signal en. It must output a glitch-free gated clock gated_clk. To achieve this without glitches, the module must internally latch the en signal while the clock is low, and hold that latched value while the clock is high. The final gated_clk output is the logical AND of the original clock and the latched enable signal.

• Clock edge: The internal latch must be transparent when clk is low (clk == 0).
• Reset type: None. The circuit operates continuously based on clock levels.
• Priority: The latch captures en continuously while clk is low. When clk transitions high, the last value of en is held safely.
• Output: gated_clk is the combinational AND of clk and the internal latch output.

Phase 1 (clk=0): en=0 → internal latch=0, gated_clk=0 Phase 2 (clk=1): en=1 → internal latch=0 (held), gated_clk=0 (glitch masked) Phase 3 (clk=0): en=1 → internal latch=1, gated_clk=0 Phase 4 (clk=1): en=0 → internal latch=1 (held), gated_clk=1 (keeps clock high for full half-cycle) Phase 5 (clk=0): en=0 → internal latch=0, gated_clk=0

{ "signal": [
  { "name": "clk",       "wave": "01010101" },
  { "name": "en",        "wave": "01...0.." },
  { "name": "latch_en",  "wave": "0.1...0." },
  { "name": "gated_clk", "wave": "0..1010." }
], "head": { "text": "Enable toggling during clock high is safely masked by the latch." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Continuous clock signal | | en | input | 1 | Clock enable signal | | gated_clk | output | 1 | Glitch-free gated clock |

Constraints

• You must infer a negative-level-sensitive latch (transparent when clk is 0).
• Do not use edge-triggered flip-flops (posedge or negedge).
• Output gated_clk must be the combinational AND of clk and the latched enable.
• No asynchronous resets are used in this module.

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