Combinational Chain Reordering
A multiply-accumulate building block in a DSP pipeline evaluates the expression Y = (A + B) * C. The addition result feeds directly into the multiplier input within the same combinational stage. This pattern appears in FIR filter coefficients, digital mixing operations, and fixed-point arithmetic units where two operations must collapse into a single pipeline stage with zero extra latency.
The solution module computes Y = (A + B) * C from 4-bit inputs and drives an 8-bit output. The result must be available combinationally with no clock or latency.
Simulation shows Y = 0 when A = 1, B = 1, C = 1 is first applied. The final output lags the inputs by a simulation delta cycle, evaluating using an outdated intermediate value. Inspect the code and correct the fault.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | A | input | 4 | First addend | | B | input | 4 | Second addend | | C | input | 4 | Multiplier | | Y | output | 8 | Result of (A+B)*C; purely combinational |
Constraints
- The output must be strictly combinational; no clock, no flip-flops, no latches.
- Do not change the module interface or port list.
- All assignments within the combinational block must use the correct assignment operator for combinational logic.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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