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Codiode/Problems/Combinational Logic

Conditional Assignment Cascades

MediumVerilog / SystemVerilogBuild

Network switches and arithmetic logic units frequently route data from multiple sources to a single destination based on strict priority rules. A priority multiplexer ensures that critical data paths take precedence over background traffic without requiring complex sequential logic or explicit if statements inside an always block.

This module receives three 8-bit data buses and two control flags. It outputs exactly one of the three data buses based on a strict priority scheme. The first flag has the highest priority and routes the first data bus. The second flag has the second highest priority and routes the second data bus. If neither flag is asserted, the third data bus is routed to the output as a default fallback.

This routing logic must evaluate continuously and update immediately whenever any input changes.

| Signal | Direction | Width | Description | | :--- | :--- | :--- | :--- | | data_a | input | 8 | First data source; routed to output if sel_a is 1 | | data_b | input | 8 | Second data source; routed to output if sel_b is 1 and sel_a is 0 | | data_c | input | 8 | Default data source; routed to output if both sel_a and sel_b are 0 | | sel_a | input | 1 | Highest priority selection flag | | sel_b | input | 1 | Secondary priority selection flag | | out_data | output | 8 | Selected data output |

Constraints

  • The design must be strictly combinational; no registers or clocks are involved.
  • sel_a has absolute priority over sel_b; if both are 1 simultaneously, data_a must be routed to the output.
  • The output must update immediately upon any change to the data or selection inputs.
  • Do not use an always block; implement the logic using continuous assignment.

Topics

CombinationalMultiplexersOperators

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