Constant Multiplier Optimization
Digital signal processing pipelines often require scaling data by fixed coefficients. Instead of instantiating a full generic multiplier, synthesis tools can optimize multiplication by a constant into a dedicated tree of adders and shifters, drastically reducing logic utilization and critical path delay.
The module receives an 8-bit unsigned integer input and multiplies it by the fixed decimal constant 123. The output must be a 15-bit unsigned integer representing the full-precision product of the input and the constant.
This is a purely combinational circuit. There is no clock or reset. The output must update immediately based on the current input.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | din | input | 8 | Unsigned multiplicand. | | dout | output | 15 | Unsigned product of din and 123. |
Constraints
- The design must be purely combinational; no latches or flip-flops may be inferred.
- The output
doutmust be exactly wide enough to hold the maximum possible value (255 * 123 = 31365), which requires 15 bits. - The input is treated as an unsigned integer.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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