Controllability Bottlenecks
Automatic Test Pattern Generation relies on controlling and observing internal nodes to detect manufacturing defects. The circuit diagram shows an 8-input AND gate U1 with primary inputs A[7:0] driving an internal node N1. Node N1 connects to one input of a 2-input XOR gate U2. The second input to U2 is a primary input B. The output of U2 drives the primary output Y. Identify the probability of setting specific logic values at N1 and determine how this bottleneck affects downstream fault activation.
Constraints
- Inputs
A[7:0]andBare driven by a pseudo-random pattern generator. - Each primary input has an independent 0.5 probability of being logic 1.
- Faults are modeled as standard single stuck-at faults.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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