Dead Code Elimination
Conditional processing blocks use enable signals to prevent unnecessary toggling and save power.
Expected behavior:
| A | B | Sel | Y | |-----|-----|-------|-----| | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 1 |
Synthesis logs show zero logic cells generated for the active processing block. Simulation shows Y = 0 for input A=1, B=1, Sel=1. The active path is dead and the output remains stuck at zero. Inspect the circuit and correct the fault.
Constraints
- Do not alter the core logic gates computing the active path.
- Fix the fault in the condition logic driving the output multiplexer or AND gate.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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