Debug 1:4 Demultiplexer
A 1-to-4 demultiplexer routes a single data input to one of four output lines based on a 2-bit select signal. The unselected outputs must remain low.
Expected behavior:
| D | S1 | S0 | Y3 | Y2 | Y1 | Y0 | |-----|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Simulation shows Y0 = 1 for input D=0, S1=0, S0=0. The circuit passes all tests where D=1, but fails to drive the selected output to 0 when D=0.
Inspect the circuit and correct the fault.
Constraints
- Do not alter the input or output port definitions.
- Ensure the fix uses standard logic gates to route the data signal correctly.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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