Debug: always_ff Sensitivity List Rejection
A D-type flip-flop with asynchronous active-high reset and a synchronous clock-enable stores a single configuration bit in a register bank. Clock-enable flip-flops are the standard building block for gating storage updates without inserting actual clock gates, which are hazardous to place manually. The flip-flop uses SystemVerilog's always_ff construct, which enforces strict rules on sensitivity list contents to prevent simulation and synthesis mismatches.
The solution module captures d on the rising clock edge when en is asserted. When rst is asserted it clears q to 0 asynchronously regardless of the clock or enable. When en is de-asserted and rst is low, q holds its current value.
Simulation fails during the compilation phase. The compiler rejects the module definition and halts with a syntax error. Inspect the code and correct the fault.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Asynchronous active-high reset; q goes to 0 immediately when asserted | | en | input | 1 | Synchronous clock enable; q captures d on rising clock edge only when en=1 | | d | input | 1 | Data input | | q | output | 1 | Registered output; resets to 0 |
Constraints
- Clock is positive-edge triggered.
- Reset is asynchronous and active-high; it takes priority over everything else.
- Enable is synchronous; it belongs in the procedural body, not the sensitivity list.
- When
en = 0andrst = 0,qholds its value. - Output
qis registered. - The module must use
always_ff.
Topics
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