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Codiode/Problems/Combinational Logic

Debug Combinational: ALU Carry Chain Disconnect

HardLogic CircuitDebug

A 4-bit ripple carry adder computes the arithmetic sum of two 4-bit values and a carry-in bit.

Expected behavior:

The circuit must output the 4-bit Sum and 1-bit Cout representing the exact arithmetic addition of the 4-bit inputs A and B, plus the 1-bit input Cin.

Simulation shows correct results for several additions. The test case for A=3, B=4, and Cin=0 correctly produces Sum=7. The test case for A=7, B=1, and Cin=0 fails. The circuit outputs Sum=0 instead of the expected Sum=8. Inspect the circuit and correct the fault.

Constraints

  • Do not modify the input or output pins.
  • Maintain the ripple carry architecture rather than replacing it with a single high-level arithmetic block.

Topics

combinationalarithmeticadderdebug

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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