Debug Combinational: Incorrect Decoder Enable
Address decoders map binary addresses to specific memory banks or hardware devices. A 3-to-8 decoder takes a 3-bit input (A2, A1, A0) and activates exactly one of its eight outputs (Y0 through Y7).
Expected behavior:
| A2 | A1 | A0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 | |------|------|------|------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Simulation shows that the circuit works correctly when A2=0, but fails when A2=1. For input A2=1, A1=0, A0=0, the circuit outputs Y4=1 and Y0=1 simultaneously. The lower half of the decoder is not being disabled correctly.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the internal logic of the two 2-to-4 decoder blocks.
- The final circuit must use only standard logic gates to route the enable signals.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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