Debug Combinational: Multiplexer Select Line Reversal
A 4-to-1 multiplexer routes one of four data lines to a single output based on a 2-bit control signal, serving as a fundamental component in datapath routing.
Expected behavior:
| S1 | S0 | Out | |------|------|-------| | 0 | 0 | D0 | | 0 | 1 | D1 | | 1 | 0 | D2 | | 1 | 1 | D3 |
Simulation shows Out = 1 for inputs D3=0, D2=1, D1=0, D0=0, S1=0, S0=1. The expected output is 0. Additionally, Out = 1 is observed when D3=0, D2=0, D1=1, D0=0, S1=1, S0=0, which should also output 0.
Inspect the circuit and correct the fault.
Constraints
- Do not add new logic gates to the circuit.
- The circuit must remain purely combinational.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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