Debug Combinational: Swapped Logic Gates
A majority voter circuit ensures fault tolerance in redundant systems by outputting 1 only when at least two of its three inputs are 1.
Expected behavior:
| A | B | C | Y | |-----|-----|-----|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
Simulation shows Y = 0 for input A=1, B=1, C=0 and Y = 1 for input A=0, B=0, C=0. The outputs for these test cases are incorrect. Inspect the circuit and correct the fault.
Constraints
- Replace only the single faulty component.
- Do not add new gates or alter the fundamental wiring architecture of the circuit.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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