Debug Register File Structural Hazard
A register file stores processor state and must support simultaneous reading and writing to maintain pipeline throughput.
Expected behavior:
The register file has one synchronous write port (WAddr, WData, WE, Clk) and one asynchronous read port (RAddr, RData). To prevent read-after-write hazards in the same cycle, the circuit must bypass write data directly to the read port when the addresses match.
| WE | WAddr == RAddr | RData Output | |------|------------------|----------------| | 0 | X | Stored data at RAddr | | 1 | 0 | Stored data at RAddr | | 1 | 1 | WData (Bypassed) |
Simulation shows RData outputs the old stored value instead of the new WData during a simultaneous read and write to the same address. Specifically, when writing WData = 9 to WAddr = 1 while reading RAddr = 1, RData outputs the previously stored value 5 instead of the expected 9.
Inspect the circuit and correct the fault.
Constraints
- Read operations must remain strictly combinational.
- Write operations to the internal registers must remain synchronous to the rising edge of
Clk. - Do not replace the core register storage components.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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