Debugging Memory Inference Failures
A 4-word by 4-bit memory block stores data for a processing pipeline and must map to dedicated Block RAM (BRAM) to conserve logic resources.
Expected behavior:
The memory writes the 4-bit din to the 2-bit addr synchronously when we is 1. The memory continuously outputs the data at addr to dout. The system reset rst must not clear the memory array, as BRAM primitives do not support array-level resets.
The synthesis toolchain reports that the memory array is being built from discrete flip-flops, exhausting available logic resources. Simulation shows that asserting rst clears the stored data. After writing din = 5 to addr = 1 and toggling rst, reading addr = 1 yields dout = 0 instead of 5. Inspect the circuit and correct the fault.
Constraints
- The memory array must retain its data during a system reset.
- Do not modify the write enable logic.
- Address and data widths must remain unchanged.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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