Debug Sequential: Ring Counter Invalid State Lockup
A 4-bit ring counter circulates a single active high bit through four flip-flops on each clock cycle.
Expected behavior:
Upon asserting the Reset signal, the counter initializes to Q3 Q2 Q1 Q0 = 0001. Subsequent clock edges shift the active bit left: 0010, 0100, 1000, and back to 0001.
Simulation shows Q3 Q2 Q1 Q0 = 0000 after Reset is asserted. Following clock edges produce no change in the output. The initialization state is incorrect.
Inspect the circuit and correct the fault.
Constraints
- Do not add new flip-flops or extra logic gates.
- Modify only the reset and preset routing for the existing flip-flops.
- Maintain the existing clock and data connections between the flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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