Debug Sequential: Shift Register Direction Reversal
Serial protocol interfaces like SPI or UART rely on shift registers to transmit data in the correct bit order. A 4-bit serial-in, parallel-out shift register accepts a serial input DataIn and shifts it from the least significant bit Q0 to the most significant bit Q3 on each clock cycle.
Expected behavior:
| Cycle | DataIn | Q3 | Q2 | Q1 | Q0 | |-------|----------|------|------|------|------| | 1 | 1 | 0 | 0 | 0 | 1 | | 2 | 1 | 0 | 0 | 1 | 1 | | 3 | 0 | 0 | 1 | 1 | 0 | | 4 | 1 | 1 | 1 | 0 | 1 |
Simulation shows that after four clock cycles with the input sequence 1, 1, 0, 1, the final output state is Q3=1, Q2=0, Q1=1, Q0=1 instead of the expected values. The output data is corrupted. Inspect the circuit and correct the fault.
Constraints
- Do not add additional flip-flops or logic gates.
- Modify only the wiring between the existing components.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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