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Codiode/Problems/FSM Design

Debugging Handshake Deadlock

HardLogic CircuitDebug

A standard valid-ready handshake protocol transfers data between a sender and receiver without dropping packets.

Expected behavior:

| has_data | ready | valid | |------------|---------|---------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 1 |

Simulation shows valid = 0 for input has_data = 1, ready = 0. The testbench times out waiting for valid to assert before it asserts ready. Inspect the circuit and correct the fault.

Constraints

  • The valid signal must depend only on the availability of data to send.
  • Do not create combinatorial loops or circular dependencies between valid and ready.

Topics

FSMDeadlockHandshakeAXI

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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