Sequence Detector 101 (FSM)
Serial protocol receivers watch a single data line for framing patterns. This detector raises z for one cycle whenever the bit stream on x completes the pattern 1 0 1, sampled on the rising edge of clk. Detection overlaps: the trailing 1 of one match can start the next.
z is a Moore output: it is high only while the machine sits in the state reached after seeing 1 0 1. rst returns the machine to its idle state.
Example stream (one bit per clock): x = 1 0 1 1 0 1 raises z after the 3rd bit and again after the 6th bit.
Constraints
- Use a single FSM node. Define states, transitions, and the Moore output
zin the FSM editor. - Detection must overlap: after recognizing 1 0 1, a following 0 1 reuses the trailing 1.
zdepends on state only, never directly on the currentx(Moore, not Mealy).
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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