Decoder via Shift Operator

Memory-mapped peripherals and register files heavily rely on address decoders to route enable signals to specific endpoints. While a traditional approach uses verbose case statements to map inputs to outputs, modern synthesis tools perfectly optimize a left-shift operation into the exact same hardware structure. Using the shift operator saves lines of code, prevents copy-paste errors, and clearly communicates the designer's intent to the synthesis tool.

The module takes a 3-bit selection input and produces an 8-bit one-hot output. When the enable signal is asserted, the single output bit corresponding to the selection value is set to 1, while all other bits remain 0. If the enable signal is de-asserted, all output bits are forced to 0 regardless of the selection input.

This is a purely combinational circuit with no clock or reset signals.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | en | input | 1 | Active-high enable; forces out to 0 when low | | sel | input | 3 | Binary selection input determining which bit to assert | | out | output | 8 | One-hot decoded output |

Constraints

• The circuit must be purely combinational.
• The solution must utilize the Verilog left-shift operator (<<) to infer the decoding logic.
• Do not use case statements or large if-else chains.
• When en is 0, out must evaluate to exactly 8'b00000000.

Topics

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