Encoding a Counter as an FSM
Hardware synthesizers map arithmetic addition operators to dedicated adder cells, which consumes unnecessary area for small sequences that are not a power of two. Representing a small counter as a finite state machine allows the synthesis tool to optimize the next state logic directly into simple combinational gates without instantiating a full adder.
This module operates as a modulo 5 counter with an enable control. Instead of using the addition operator, the sequence is defined explicitly using states. When enabled, the counter advances through the sequence 0, 1, 2, 3, 4 and wraps immediately back to 0. When disabled, the counter holds its current value.
The circuit uses a positive edge triggered clock and an active low asynchronous reset. On reset, the counter state initializes to 0. If the enable signal is asserted, the count advances on the clock edge. If the enable is de-asserted, the count remains unchanged.
Cycle 1: rst_n=0 → count=0 Cycle 2: rst_n=1, en=1 → count=1 Cycle 3: en=1 → count=2 Cycle 4: en=0 → count=2 (hold) Cycle 5: en=1 → count=3 Cycle 6: en=1 → count=4 Cycle 7: en=1 → count=0 (wrap)
flowchart LR
RESET(( )) -->|reset| S0
S0((0)) -->|en=1| S1((1))
S0 -->|en=0| S0
S1 -->|en=1| S2((2))
S1 -->|en=0| S1
S2 -->|en=1| S3((3))
S2 -->|en=0| S2
S3 -->|en=1| S4((4))
S3 -->|en=0| S3
S4 -->|en=1| S0
S4 -->|en=0| S4| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive edge triggered clock | | rst_n | input | 1 | Asynchronous active low reset; count goes to 3'b000 when asserted | | en | input | 1 | Enable; counter advances on posedge clk while en=1 | | count | output | 3 | Current count value; resets to 3'b000 |
Constraints
- Clock edge is
posedge, reset is asynchronousnegedge. - The counter must strictly output values in the range 0 to 4.
- Output
countis a registered 3-bit value. - Do not use the addition operator; implement the next state transitions using a
casestatement. - Any invalid state must recover to 0 on the next clock cycle.
Topics
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