Endianness Swapping

Network protocols typically transmit data in big-endian format, while modern microprocessors often store data in little-endian format. A hardware bridge between a CPU and an Ethernet MAC must swap the byte order of 32-bit words on the fly to ensure data is interpreted correctly by both domains. Because this operation simply reorders existing data bits, it is a pure routing operation that should synthesize entirely into wire assignments without consuming any logic gates.

The module receives a continuous 32-bit input word and must reverse the order of its four bytes. The most significant byte of the input becomes the least significant byte of the output, the second byte becomes the third, the third becomes the second, and the least significant byte becomes the most significant byte.

This is a purely combinational circuit. There is no clock, no reset, and no sequential state.

Example trace: • data_in = 32'hAABBCCDD → data_out = 32'hDDCCBBAA • data_in = 32'h12345678 → data_out = 32'h78563412

| Signal | Direction | Width | Description | |------------|-----------|-------|-------------| | data_in | input | 32 | The 32-bit input word to be byte-swapped | | data_out | output | 32 | The 32-bit output word with reversed byte order |

Constraints

• The circuit must be purely combinational.
• Do not instantiate any flip-flops, latches, or sequential logic.
• Byte 3 (bits 31:24) of the input maps to Byte 0 (bits 7:0) of the output.
• Byte 2 (bits 23:16) of the input maps to Byte 1 (bits 15:8) of the output.
• Byte 1 (bits 15:8) of the input maps to Byte 2 (bits 23:16) of the output.
• Byte 0 (bits 7:0) of the input maps to Byte 3 (bits 31:24) of the output.

Topics

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