Expensive Operator in a Loop
A hardware checksum module calculates the running sum of a data stream to verify data integrity during transmission.
Expected behavior: The module must accumulate an 8-bit Data input into an 8-bit Checksum output on every rising edge of Clk when Enable is high. The accumulation must clear to zero when Reset is high.
Simulation shows the circuit fails the maximum area constraint. The synthesis report lists sixteen instantiated 8-bit adders instead of the allowed one. Furthermore, the sequential test bench fails: when Enable is high and Data is provided over consecutive clock cycles, the output Checksum remains static and does not accumulate the incoming values.
Inspect the circuit and correct the fault.
Constraints
- The design must use exactly one 8-bit adder.
- The
Checksumoutput must be driven by a sequential register. - Do not use combinational unrolled loops to process the data.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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