Fault Dominance and Collapsing
Automatic Test Pattern Generation tools like Tetramax rely on fault dominance and equivalence collapsing to minimize the number of test vectors required for manufacturing sign-off.
The circuit below is a standard AND-OR-Invert (AOI22) logic block with four inputs A, B, C, D and one output Y. The logic function implemented is Y = ~((A * B) + (C * D)). The intermediate wire between the first AND gate and the NOR gate is w1. The intermediate wire between the second AND gate and the NOR gate is w2.
Analyze the single stuck-at fault models for this structure. Determine the collapsed fault set by identifying equivalent and dominant faults across the logic gates. Calculate the absolute minimum number of test vectors required to achieve 100 percent single stuck-at fault coverage.
Constraints
- Assume a single stuck-at fault model where only one node can be Stuck-At-0 (SA0) or Stuck-At-1 (SA1) at any given time.
- Assume the logic gates used are ideal primitives: two 2-input AND gates feeding into one 2-input NOR gate.
- Test vectors are formatted as 4-bit strings in the order
ABCD.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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