Fault Equivalence in Basic Gates
Manufacturing defects require physical testing, but testing every possible fault in a modern chip is computationally impossible. Design for Testability (DFT) relies on fault collapsing to group faults that produce identical output behaviors into equivalence classes.
The circuit below is a standard 4-input NAND gate with inputs A, B, C, D and output Y. A stuck-at fault model assumes a single node is permanently tied to logic 0 (SA0) or logic 1 (SA1).
Analyze the fault equivalence classes for this gate. Determine exactly which input faults are structurally indistinguishable from the output Y being stuck-at-1.
Constraints
- Assume a single stuck-at fault model.
- Only structural equivalence is considered.
- The gate is an ideal combinational element with no timing defects.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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