Feedback Multiplexer Optimization
Hardware synthesizers infer feedback paths to preserve register state across clock cycles when an explicit assignment is missing. The provided schematic shows the synthesized netlist of a digital state machine. The data path includes a register R1, a two-to-one multiplexer MUX_A, and control signals stall and next_val.
Analyze the data path to identify how the state is maintained during a stall condition. Determine the Boolean logic governing the select line of the feedback multiplexer.
Constraints
- The circuit operates on a single clock domain
- All multiplexers are standard two-to-one components
- The stall signal is active-high
Topics
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