FIFO Simultaneous Read Write when Full

Data queues between processing stages often encounter bottleneck conditions. When a standard FIFO buffer reaches maximum capacity, it asserts its full flag and blocks incoming writes, forcing the upstream transmitter to stall. However, high-throughput systems cannot afford to drop data or stall when a read operation occurring in the same clock cycle will free up space. In these systems, the FIFO write logic must look ahead to the read enable signal to maintain maximum throughput.

The module is a synchronous FIFO with a depth of 4 and an 8-bit data width. It maintains full and empty status flags. When the FIFO is full, an incoming write operation is normally ignored. However, if a read operation occurs simultaneously, the read removes an item and frees a slot, allowing the write to be accepted in the exact same cycle. The full flag remains asserted in the next cycle because the net change in item count is zero.

Similarly, simultaneous read and write when the FIFO is not full simply processes both operations. If a simultaneous read and write occurs when the FIFO is empty, the write is accepted but the read is ignored, as there is no valid data to read yet. A read from an empty FIFO is always ignored, and the read data output simply holds its previous value.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets pointers, count, and flags | | wr_en | input | 1 | Write enable; asserts when upstream has data to push | | wr_data | input | 8 | Data to be written into the FIFO | | rd_en | input | 1 | Read enable; asserts when downstream is ready to pop data | | rd_data | output | 8 | Data read from the FIFO; updates only on a valid read; resets to 8'h00 | | full | output | 1 | Asserts to 1 when the FIFO contains 4 items; resets to 0 | | empty | output | 1 | Asserts to 1 when the FIFO contains 0 items; resets to 1 |

Constraints

• Clock edge: posedge clk
• Reset: asynchronous active-low rst_n
• Outputs on reset: full=0, empty=1, rd_data=8'h00
• The FIFO depth is exactly 4 and data width is exactly 8 bits
• A simultaneous read and write when full=1 must accept the write and execute the read
• A simultaneous read and write when empty=1 must accept the write and ignore the read
• A read from an empty FIFO must not modify internal pointers, and rd_data must hold its previous value
• A write to a full FIFO with no simultaneous read must not modify internal pointers or memory

Topics

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