Synchronous Single Port RAM

High-density on-chip storage relies on dedicated SRAM blocks rather than discrete flip-flops to optimize silicon area and power consumption. The synchronous single-port RAM is the fundamental building block for these storage structures, providing a shared interface for both read and write operations that executes one transaction per clock cycle.

The memory array contains 16 words, with each word being 8 bits wide. Access to the memory is governed by a chip enable signal and a write enable signal. When the chip is enabled, the memory performs a write operation if the write enable is asserted, or a read operation if it is de-asserted.

All operations are synchronous to the positive edge of clk. When a write operation occurs, the memory must exhibit write-first behavior, meaning the output dout updates simultaneously to reflect the newly written data. When a read operation occurs, the memory contents at addr are driven to dout. When the chip enable is de-asserted, the memory ignores all inputs and dout strictly holds its previous value. There is no reset pin for the memory array.

Cycle 1: ce=1, we=1, addr=4'h5, din=8'hAA → dout=8'hAA (Write to addr 5) Cycle 2: ce=0, we=0, addr=4'h0, din=8'h00 → dout=8'hAA (Hold previous output) Cycle 3: ce=1, we=0, addr=4'h5, din=8'h00 → dout=8'hAA (Read from addr 5)

{ "signal": [
  { "name": "clk",  "wave": "p..." },
  { "name": "ce",   "wave": "101." },
  { "name": "we",   "wave": "100." },
  { "name": "addr", "wave": "===.", "data": ["5", "0", "5"] },
  { "name": "din",  "wave": "===.", "data": ["AA", "00", "00"] },
  {},
  { "name": "dout", "wave": "x==.", "data": ["AA", "AA"] }
], "head": { "text": "Write-first memory access followed by hold and read." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | ce | input | 1 | Chip enable; active-high | | we | input | 1 | Write enable; active-high | | addr | input | 4 | Memory address for read and write operations | | din | input | 8 | Data input for write operations | | dout | output | 8 | Data output; updates on posedge clk |

Constraints

• The memory array must be exactly 16 words deep and 8 bits wide.
• All operations must be synchronous to the positive edge of clk.
• When we is asserted, the memory must exhibit write-first behavior and forward the new data to dout.
• When ce is de-asserted, dout must hold its exact previous value.
• Do not use asynchronous resets or attempt to initialize the memory array to zero.

Topics

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