ROM Inference via Case
Digital signal processing pipelines often require small lookup tables for trigonometric functions. When these tables are shallow, mapping them to distributed logic rather than dedicated block RAM saves routing resources and prevents pipeline stalls.
The module acts as an asynchronous read only memory containing a 16-sample sine wave. It receives a 4-bit address representing the phase index and outputs the corresponding 8-bit amplitude. The output must react immediately to any change in the address input using purely combinational logic.
The memory must contain the following exact values for each address:
addr= 0:data= 128addr= 1:data= 176addr= 2:data= 218addr= 3:data= 246addr= 4:data= 255addr= 5:data= 246addr= 6:data= 218addr= 7:data= 176addr= 8:data= 128addr= 9:data= 79addr= 10:data= 38addr= 11:data= 9addr= 12:data= 0addr= 13:data= 9addr= 14:data= 38addr= 15:data= 79
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | addr | input | 4 | Phase index for the lookup table | | data | output | 8 | Amplitude value corresponding to the phase index; purely combinational |
Constraints
- The circuit must be purely combinational with no clock or reset dependencies
- All 16 possible input addresses must map to the exact specified integer values
- The design must not infer latches; all branches must be explicitly defined
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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