Power of Two Alignment
Memory controllers and direct memory access (DMA) engines frequently require memory addresses to be aligned to specific data burst boundaries. When a processor issues an unaligned memory request, the hardware must calculate the nearest aligned base address to initiate the fetch. Aligning an address to a power of two boundary requires truncating the least significant bits of the address bus.
This module calculates the 8-byte aligned base address for any given 32-bit input address. It computes the largest address that is less than or equal to the input address and is a perfect multiple of eight.
This is a purely combinational circuit. Changes on the input immediately reflect on the output with no clock or reset dependencies.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | addr_in | input | 32 | Unaligned 32-bit memory address | | addr_out | output | 32 | 32-bit memory address rounded down to the nearest multiple of 8 |
Constraints
- The output
addr_outmust be purely combinational. - The module must round down to the nearest multiple of 8.
- You must not use arithmetic division or modulo operators; synthesize the logic using only bitwise operations or concatenation.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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