Four Stage Pipelined Multiplier

Combinational multipliers create deep logic paths that severely limit the maximum clock frequency of a digital system. In high-speed DSP applications, partial product accumulation is heavily pipelined to maintain high throughput and meet timing closure.

This module implements a 4-bit unsigned shift-and-add multiplier spread across four discrete pipeline stages. When valid_in is asserted, the multiplier accepts a new pair of 4-bit operands, a and b. In each of the four subsequent clock cycles, one partial product is evaluated and added to an accumulating sum. The intermediate sum, the shifted version of a, and the shifted version of b are passed to the next pipeline stage. After four clock cycles, the final 8-bit product is driven on p along with the valid_out signal.

The module operates on a posedge clk and features an asynchronous, active-low reset rst_n. On reset, all internal pipeline registers and outputs must be driven to 0. When an invalid cycle enters the pipeline (valid_in is 0), the invalid state must propagate through the stages, clearing the data registers for that stage to 0 to prevent unnecessary toggling and reduce power consumption.

Cycle-by-cycle trace for two back-to-back multiplications: Cycle 1: rst_n=0 → valid_out=0, p=0 Cycle 2: rst_n=1, valid_in=1, a=3, b=5 → valid_out=0, p=0 (Stage 1 samples inputs) Cycle 3: valid_in=1, a=2, b=2 → valid_out=0, p=0 (Stage 1 samples new inputs, Stage 2 processes 3x5) Cycle 4: valid_in=0, a=0, b=0 → valid_out=0, p=0 (Stage 3 processes 3x5, Stage 2 processes 2x2) Cycle 5: valid_in=0, a=0, b=0 → valid_out=0, p=0 (Stage 4 processes 3x5, Stage 3 processes 2x2) Cycle 6: valid_in=0, a=0, b=0 → valid_out=1, p=15 (3x5 completes, Stage 4 processes 2x2) Cycle 7: valid_in=0, a=0, b=0 → valid_out=1, p=4 (2x2 completes) Cycle 8: valid_in=0, a=0, b=0 → valid_out=0, p=0 (Pipeline empty)

{ "signal": [
  { "name": "clk", "wave": "p......." },
  { "name": "rst_n", "wave": "01......" },
  { "name": "valid_in", "wave": "0110...." },
  { "name": "a", "wave": "====....", "data": ["0", "3", "2", "0"] },
  { "name": "b", "wave": "====....", "data": ["0", "5", "2", "0"] },
  {},
  { "name": "valid_out", "wave": "0....110" },
  { "name": "p", "wave": "=....===", "data": ["0", "15", "4", "0"] }
], "head": { "text": "Two back-to-back multiplications propagating through the 4-stage pipeline." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all registers go to 0 when asserted | | valid_in | input | 1 | Asserted when a and b contain valid operands | | a | input | 4 | Multiplicand | | b | input | 4 | Multiplier | | valid_out | output | 1 | Asserted when p contains a valid product | | p | output | 8 | Final accumulated product |

Constraints

• Clock edge: posedge clk
• Reset: asynchronous, active-low (rst_n).
• All pipeline registers (including internal accumulators and shift registers) must be driven to 0 on reset.
• The pipeline depth must be exactly 4 cycles from valid_in to valid_out.
• When the valid bit for a given stage is 0, the data registers (accumulator, shifted a, shifted b) for that stage must be cleared to 0.
• Outputs valid_out and p must be registered (driven directly by flip-flops).

Topics

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