CodiodeCodiode
Home
Problem Solving
Skill Tracks
My Assignments
Contests
Leaderboard
Community
Settings
Codiode/Problems/Arithmetic

Parameterized Sign Extension Unit

MediumVerilog / SystemVerilogBuild

Instruction decoders in modern microprocessors must extract and sign-extend immediate values from instruction words. Since different instruction formats encode immediates of varying lengths, the datapath requires a dynamic sign extension unit that can adjust the sign bit location on the fly based on the current instruction type.

The module receives an input bus in and a dynamic control signal valid_length indicating the actual bit width of the valid signed integer contained in the lower bits of in. The circuit must extract this integer, identify its sign bit located at index valid_length - 1, and sign-extend it to the full OUT_WIDTH. Any bits in in above valid_length - 1 are ignored. If valid_length is 0, the output out must be driven to all zeros.

This circuit is purely combinational. There is no clock or reset.

Module Parameters: • IN_WIDTH: Maximum width of the input bus (Default: 32) • OUT_WIDTH: Width of the extended output bus (Default: 32) • LEN_WIDTH: Width of the length control signal (Default: 6)

| Signal | Direction | Width | Description | |---|---|---|---| | in | input | IN_WIDTH | Raw input data containing the integer to be sign-extended | | valid_length | input | LEN_WIDTH | The bit length of the valid signed integer inside in | | out | output | OUT_WIDTH | The sign-extended output value |

Worked Trace: • Input: valid_length = 8, in = 32'h0000_008F • The valid integer is 8 bits wide: 8'h8F (binary 1000_1111). • The sign bit is bit 7, which is 1. • The upper bits of out are padded with 1s. • Result: out = 32'hFFFF_FF8F.

Constraints

  • The design must be purely combinational.
  • When valid_length is 0, out must evaluate to 0.
  • The behaviour when valid_length exceeds IN_WIDTH is undefined and will not be tested.
  • The upper bits of in beyond index valid_length - 1 must not affect the output.

Topics

ArithmeticCombinational LogicParameters

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

Sign in to solveSee what Pro unlocks

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Related problems

  • Binary to Gray Code DatapathEasy
  • Fixed Point Multiplication with SaturationHard
  • Absolute Value with Bit GrowthMedium
  • 8 bit Basic ALU with FlagsEasy
  • 8-bit Combinational PopcountMedium
  • 8-bit Logical Barrel ShifterMedium
  • 16-bit Arithmetic Barrel ShifterHard
  • Parameterized ALU with Safe DefaultsMedium

Browse all problems · Learning tracks