Q4.4 and Q2.6 Addition
Fixed-point arithmetic in digital signal processing requires manual alignment of binary radix points. Misaligned additions produce garbage data, as hardware adders blindly sum bits by their index without understanding their fractional weight.
This module takes two unsigned fixed-point values with different formats and computes their sum. The first input uses a Q4.4 format (4 integer bits, 4 fractional bits) and the second uses a Q2.6 format (2 integer bits, 6 fractional bits). The module aligns their radix points and produces a Q5.6 result (5 integer bits, 6 fractional bits) to guarantee no precision loss or overflow.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Unsigned Q4.4 value | | b | input | 8 | Unsigned Q2.6 value | | c | output | 11 | Unsigned Q5.6 sum of a and b |
Constraints
- The circuit must be purely combinational.
- Both inputs and the output must be treated as unsigned values.
- The radix points must be perfectly aligned before addition by padding the fractional bits of the Q4.4 input with zeros.
- The integer bits must be padded with zeros to match the 11-bit target width before addition to prevent overflow.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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