Twos Complement Overflow Detection
Processors rely on Arithmetic Logic Units (ALUs) to perform basic math operations and set status flags. When adding signed numbers, the system must detect if the result exceeds the representable range, triggering an overflow exception or setting an overflow flag.
Compute the sum of two 8-bit two's complement integers. Along with the sum, output a single-bit overflow flag that asserts when the addition results in an arithmetic overflow. A common anti-pattern is to zero-extend or sign-extend the operands to 9 bits, perform the addition, and compare the upper bits. This approach wastes logic. Instead, derive the overflow flag using only the sign bits (the most significant bits) of the two operands and the resulting sum.
This is a purely combinational circuit. There is no clock or reset. The output must reflect the inputs immediately.
Example 1: a = 127 (0x7F), b = 1 (0x01). sum = 128 (0x80). overflow = 1. Example 2: a = 255 (0xFF), b = 255 (0xFF). sum = 254 (0xFE). overflow = 0. Example 3: a = 128 (0x80), b = 255 (0xFF). sum = 127 (0x7F). overflow = 1.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | First two's complement operand | | b | input | 8 | Second two's complement operand | | sum | output | 8 | Result of a + b | | overflow | output | 1 | Asserted to 1 if two's complement overflow occurs, otherwise 0 |
Constraints
- Purely combinational logic; do not infer any latches or flip-flops.
- Do not use a 9-bit intermediate adder to detect overflow; derive it directly from the sign bits (MSBs) of the inputs and the 8-bit sum.
- Operands are strictly 8-bit two's complement values.
Topics
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